Ageing Impact on a High Speed Voltage Comparator with Hysteresis
نویسندگان
چکیده
The impact of ageing on a high speed comparator with hysteresis in 65-nm CMOS technology using SPICE simulations is investigated. The comparator has been designed to offer immunity to single event transients. The most sensitive transistor was subjected to single events at manufacture time and after ageing, assuming a maximum parameter drift of 10% on all PMOS transistors for 10 years. It was found that NBTI does not significantly affect the single event transient vulnerability of the comparator, at different hysteresis voltages.
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